How to fix the most common KiCad DRC errors

Before you send a board to a fab, KiCad's Design Rule Checker (DRC) is your last automated line of defence. It compares your PCB against the constraints in Board Setup — clearances, track widths, drill sizes, connectivity — and flags anything that would fail to manufacture or fail to work. Running it (and clearing it) is the difference between a board that comes back working and one that comes back scrap.

Short answer: DRC checks your layout against your design rules. Run it after every routing change and always before manufacturing. Fix every error, review every warning, and only exclude a violation once you understand why it is safe.

This guide walks through the most common KiCad DRC errors, what causes each one, and how to fix it.

How to run DRC#

There are two ways to run the check.

In the GUI: open the PCB editor and go to Inspect → Design Rules Checker. Click Run DRC. Violations appear grouped by type; click any one to jump straight to it on the board. KiCad also runs DRC live as you route, so many issues surface before you ever open the dialog.

On the command line: kicad-cli runs the same engine headlessly, which is what you want for scripting and automation.

kicad-cli pcb drc --output drc.json --format json --exit-code-violations board.kicad_pcb

The --exit-code-violations flag makes the command return a non-zero exit code when violations exist, so a build step can fail on a bad board. This is exactly how continuous integration for PCBs works — every push re-runs DRC and surfaces regressions automatically.

Where the rules come from#

Every DRC violation traces back to a constraint you can see and edit. Most live in File → Board Setup:

• Design Rules → Constraints — global minimums for clearance, track width, annular ring, hole size, and hole-to-hole spacing.
• Design Rules → Net Classes — per-net-class clearances and widths (for example a wider, higher-clearance class for power nets).
• Design Rules → Custom Rules — text-based rules for anything the dialogs do not cover.

Set these to match your fab's capabilities first. Most DRC pain comes from rules that are stricter or looser than the process you actually ordered.

Clearance violations#

Cause: two copper items — tracks, pads, zones, vias — are closer than the clearance defined for their net class, or the board's minimum clearance. This is the single most common DRC error.

Fix: click the violation to see the two offending items and the required versus actual distance. Reroute to open up space, nudge the track, or move a component. If the clearance itself is wrong — too conservative for your fab — raise or lower it in the relevant net class rather than fighting individual tracks. For copper zones, check the zone's own clearance setting, which can override the global value.

Unconnected items / unrouted nets#

Cause: two pads that share a net are not electrically joined. Either a ratsnest line was never routed, or a track ends near a pad without landing on it.

Fix: turn on the ratsnest to see the unfinished connections as thin lines. Route them. If a net looks routed but still flags, zoom in on the pad — a track that stops a few microns short reads as unconnected. In modern KiCad, hovering or selecting the net highlights the full copper path so the gap stands out. Missing intentional connections between two different nets need a net tie footprint, not a raw overlap.

Courtyard overlap#

Cause: the courtyard outlines (on F.CrtYd / B.CrtYd) of two footprints intersect, meaning the physical parts would collide or sit too close to assemble.

Fix: move the components apart until the courtyards clear. If two parts are genuinely meant to be that close and the courtyard is drawn too generously, edit the footprint's courtyard in the footprint editor — but be conservative, because courtyards exist to guarantee assembly clearance.

Silkscreen over pad / soldermask#

Cause: silkscreen (F.Silkscreen) overlaps exposed copper or a soldermask opening. Silk printed over a pad can end up on the solderable surface, causing poor joints.

Fix: move or shrink the offending reference designator or graphic so it clears the pad. Use Edit → Cleanup Graphics or reposition text manually. For dense boards, reducing silk text size or hiding non-essential designators is often the cleanest fix.

Track width / minimum width#

Cause: a track is narrower than the minimum trace width in your constraints or net class — frequently a signal routed at a default width that is finer than your fab can reliably etch.

Fix: select the track and increase its width, or update the net class so its default width is manufacturable. For current-carrying nets, size the width to the current and your fab's minimum, whichever is larger.

Annular ring / drill-to-copper#

Cause: the copper ring around a via or pad hole is thinner than the minimum annular ring, or copper sits too close to a drilled hole. Small vias with default pad sizes are the usual culprit.

Fix: increase the pad or via diameter so the ring meets the minimum, or reduce the drill if the fab allows it. Set the Minimum annular width constraint in Board Setup to your fab's spec so the check is meaningful.

Hole clearance / hole-to-hole#

Cause: two drilled holes are closer than the minimum hole-to-hole spacing. Overlapping or near-touching drills can break out during fabrication.

Fix: space the vias or pads further apart, or consolidate redundant vias. Confirm the Hole-to-hole constraint matches your fab — a common default is 0.25 mm, but your process may differ.

Edge clearance#

Cause: copper, a track, or a pad sits too close to the board edge defined on Edge.Cuts. Copper near the routed edge can be exposed or damaged during depanelization.

Fix: pull copper and components back from the outline, or widen the edge-clearance constraint if your fab supports copper closer to the edge. Watch zones especially — fill often creeps toward the board edge unless the zone clearance holds it back.

Quick reference#

Clear DRC on every revision, not just the last one#

DRC only helps if you run it consistently. It is easy to clear the check once, then introduce a clearance or width regression three commits later and never notice until the fab rejects the order. A related trap is shipping an incomplete manufacturing package — clean DRC on stale Gerbers is worse than no check at all.

That is why GoForFab runs kicad-cli pcb drc on every push, diffs the result against your last clean run, and flags any new violation before it reaches the fab — automatically, and free forever. Clear DRC once, and let the pipeline keep it clear.